1. Field of the Invention
The present invention relates to a semiconductor device and a designing method thereof, and more particularly relates to a semiconductor device having a plurality of wiring layers and a designing method thereof.
2. Description of Related Art
In order to fulfill user requirements, logic circuits formed on a semiconductor device such as DRAM (Dynamic Random Access Memory) are becoming increasingly complicated. Therefore, a multi-layered structure is employed for wiring on a semiconductor substrate. In addition, wiring density in each of the wiring layers has been increasing (see Japanese Patent Application Laid-open No. H9-74175).
In case of a multi-layered structure, contact conductors that connect wiring layers penetrate inter-layer insulating layers. Some of the contact conductors connect wiring layers that are two or more wiring layers apart in the multi-layered structure. In this case, intermediate wiring layers are required to be laid out to avoid the contact conductors area. For example, assume that wiring layers are laminated in the order of a first wiring layer, a second wiring layer, and a third wiring layer, and a contact conductor connects the wiring of the first wiring layer to the wiring of the third wiring layer. In this case, wiring in the second wiring layer cannot be formed in an area where the contact conductor exists, so that the wiring in the second wiring layer is required to be laid out to avoid this area.
Contact conductors connecting wiring layers that are two or more wiring layers apart are frequently used for power lines. The reason for this is as follows. Because a power line is required to be formed over a wide area and is required to have a low resistance, it is a common practice to employ an upper-layer wiring having a thick wire width. Consequently, it is necessary to connect to a power line of lower layers at a number of places, so that contact conductors used for this purpose restrict the layout of the intermediate wiring layers. This problem is explained in more detail below with reference to FIG. 8.
FIG. 8 is a schematic plan view of a wiring layout of a typical semiconductor device.
The semiconductor device shown in FIG. 8 has three wiring layers, where the uppermost wiring layer L3 has wirings 1 and 2 extending parallel to an X direction, and the lowermost wiring layer L1 has wirings 3 and 4 extending parallel to a Y direction. The wirings 1 and 3 are supplied with the same signal or the same electric potential and they are connected to each other with a contact conductor 5. Similarly, the wirings 2 and 4 are supplied with the same signal or the same electric potential and they are connected to each other with a contact conductor 6.
The wiring in a wiring layer L2 between the wiring layers L1 and L3 is not shown in FIG. 8. Although each of the wirings generally extends in the X direction or the Y direction, the contact conductors 5 and 6 have a diagonal positional relationship. Accordingly, if a predetermined margin M is secured around the contact conductors, no wiring can be formed in at least a prohibited area 7 of the wiring layer L2 shown in FIG. 8. Therefore, a wiring in the wiring layer L2 must be laid out such that it is away from the prohibited area 7.
In this manner, as the layout of the intermediate wiring layer is restricted because of contact conductors that connect wiring layers that are two or more layers apart, it is preferable that the prohibited areas are as small as possible.